The present invention relates generally to a voltage regulation subsystem and, more particularly, to regulation subsystems for microprocessor circuitry.
Microprocessor circuitry, such as SoCs conventionally include on-chip voltage regulation and a digital logic controller to regulate their voltage supply. As microprocessor circuitry develops to operate at higher frequencies and as the density of transistors on integrated circuits increases, the vastly increased number of transitions in transistor state in the limited area of each integrated circuit leads to ever greater current demand and thermal stresses. Mechanisms are therefore needed to manage power in such systems.
Recent trends towards the increased use of multi-core and SoC systems make the development and improvement of such power management mechanisms all the more urgent. It has therefore become common to supply recent generations of microprocessor circuitry with power indirectly using a voltage regulator configured to supply a suitable current and a “well-regulated” voltage while preserving desired transient response characteristics.
Conventionally voltage regulators have been implemented as components integrated on the same chip as the microprocessor core, where each core has its own voltage control. The voltage regulator will also typically take the supply voltage and step it down to a lower voltage, as required by the microprocessor core. In this respect the voltage regulator implements a “buck converter” or a Low Drop Out (LDO) linear regulator, stepping-down the supply voltage to a DC voltage required by the core. Voltage regulators need to be adapted to respond to changes of load current at time scales similar to those changes. Other performance constraints include efficiency (i.e., minimization of losses) and power density.
Load current in SoC systems can change whenever a microprocessor, or other circuit component, enters an inactive (i.e., “sleep”) mode or an active mode (i.e., so-called e-states and c-states). Additionally, certain microprocessor architectures also power gate or switch off the power for different domains as required. Changes in load current can themselves induce transient effects (often referred to as “transients”). The rate of changes in load levels for more recent “high transistor density” systems is high, commensurate with the higher clock speeds of these systems.
In typical implementations, voltage regulation is managed by a power management controller (PMC). PMCs conveniently also include units (i.e., digital logic controller units, DLCs) that monitor power on reset (POR) and low voltage detection (LVD) values. POR signals are generally of two types: high voltage, HV_supply_POR and low voltage, LV_supply_POR. These POR signals enable the transistors operating in high voltage (HV) logic and low voltage (LV) logic respectively. The LVD and POR indicators can be on the same supply source but the respective voltages at which they trigger may differ. For instance, with a 1.2V supply, (LV) POR threshold can be at 0.7V while LVD is at 1.08V. Voltage regulation together with POR and LVD monitoring is intended to ensure safe device operation. The LVD monitor tracks PMC supply voltage VDDREG, VDD digital core voltage supply, and VDDSYN with high precision, while the POR monitor checks main regulator supply VDDREG and VDD digital core voltage supply.
While it has become conventional to locate voltage regulators as close as possible to the most significant loads (i.e., microprocessor cores) and therefore to provide on-chip voltage regulators, there are nevertheless scenarios where “off-chip” voltage regulation may be considered. For example, when the current requirement is very high and the die area is limited.
Certain SoC systems offer both internal and external regulation modes. External regulation relies on an external regulator that works on an external bandgap. This external bandgap is a reference voltage that is factory calibrated to provide a reliable voltage over a known temperature range and supply voltage variation, say 0.62V, with some variation. Internal regulators have corresponding internal bandgap reference voltages. There can however be a non-correlation of external and internal bandgap variation over process and temperature.
Depending upon the requirements of the PMC and the regulated circuitry, the bandgap and LVD comparator may be tuned to prevent the reference from exceeding a specific threshold, say 1.15V. This is achieved by applying a known digital bit value to a comparator—commonly known as “trim”. The PMC typically includes a dedicated memory such as an EEPROM for storing a table of trim bit values. In certain circumstances, a bandgap may exceed or fail to achieve design expectations, so by selecting appropriate points on the bandgap output the effective bandgap may be tuned to match the design expectations.
During power up and reset the bandgap is typically untrimmed. The range of variation of LVD reference, which at this stage includes the untrimmed bandgap variation, is much higher than that once trimmed levels are applied. As long as the supply voltage is higher than the untrimmed LVD threshold, the use of an untrimmed bandgap allows the regulated circuitry to exit reset. In some cases, this requires the software or a user to overdrive the supply voltage at power up and reset. Untrimmed range is used before the bandgap trims get loaded from dedicated memory (i.e., flash memory). Thus, during power up and before the flash memory is read, the LVD reference variation may be high. The trim is then applied once the reset process (performed by a reset generation module, RGM) is complete. In fact, trims are applied only after the system has determined that the supply voltage exceeds the untrimmed levels of the bandgap and that LVD comparators have tripped.
To improve the performance of such external regulators in the face of non-correlation between external and internal bandgap variation, it is known to disable the PMC units that provide core LVD/HVD monitoring at first boot and/or to increase the core voltage specification to counter the untrimmed LVD levels. If the PMC units are disabled, external off-chip LVD monitors are required instead, which adds complexity and cost. If, on the other hand, core voltage is increased to counter LVD untrimmed range (while the internal LVD monitoring unit of the SoC is enabled), it leads to higher power consumption in operating mode.
In the latter option, core voltage is increased rather than attempting to reduce the untrimmed LVD level. Untrimmed LVD levels cannot be reduced as this may lead to a number of challenges arising from low supply voltage. If the untrimmed LVD levels were reduced, allowing the supply voltage to drop to a reduced level without triggering the LVD comparator, this would at some point increase power consumption. Furthermore, if the supply voltage were to go below a certain Vmin, where Vmin is the voltage at which timing has been met for the entire digital logic, timing related setup and hold violation would ensue leading to complete failure of the functional behavior of the SoC.
It is also seen that certain external regulators designed with low bandwidth, lack fast load transition capabilities. These regulators require internal circuitry (referred to as “auxiliary regulators” or AUX regulators) to support fast load transition. In cases where internal AUX regulators are used to support load transition, these AUX regulators are enabled only when the system detects that supply exceeds an LVD threshold. If untrimmed variation on the bandgap is too great, the LVD threshold (which is related to the bandgap) becomes high and hence if core voltage from external supply approaches minimum operating voltage, the supply may not exceed the LVD threshold and hence AUX regulator cannot be enabled. Furthermore, the internal bandgap variation may be completely unrelated to the external supply bandgap variation. Hence these internal AUX regulators cannot be used reliably with existing architectures for voltage regulation upon boot (power-on) or reset.
If the LVD/HVD monitoring units are not disabled at first boot (POR), i.e., before untrimmed LVD reference levels are released, it is possible the untrimmed LVD reference voltage will vary sufficiently that it exceeds the minimum supply voltage, the LVD monitor unit will not assert and the AUX regulator will remain in the “off” state—meaning that the regulated supply would never go above the LVD level and hence circuitry never exits the reset process.
It is also possible that, were the AUX regulator enabled at power on reset (POR) (the POR threshold being ˜600 mV for a 1.2V supply, say), this could result in an unwelcome electrostatic discharge (ESD) as low voltage circuitry in the PMC ramps up. The AUX regulator would operate to pull the supply voltage to operating level (i.e., 1.2V) from the POR threshold level (i.e., 0.6V) in a sudden inrush (e.g., with a time scale in the order of 200 ns). This happens because the conventional internal AUX regulator is designed to handle load transition and has a capability to inject large current to correct the voltage. This sharp jump can cause ESD protection circuits to trigger.
A further challenge arises when attempting to use known verification techniques. While internal regulator behavior is understood and load transitions may be verified using known methods, no such capability exists for external regulation mode. In such multi-regulation subsystems, currently there is therefore a requirement for a method to verify the functionality and electrical behaviors of systems having internal regulators at start-up, as well as load transition and mode transition behaviors in such systems.